- Beyond the chip hype: As India races towards a semiconductor powerhouse, IISc’s 7th India ESD Workshop asks a crucial question — can chips be made not only smarter, but resilient enough to survive the invisible electrical threats that can destroy them?
- From classroom to cleanroom: More than 250 semiconductor professionals attended the previous edition, while the 2026 programme brings students, researchers, engineers and global experts together around advanced ESD design and reliability.
- The 3D-chip challenge: Sessions will probe ESD protection in advanced CMOS, FinFETs, nanosheets, 2.5D/3D ICs, TSVs, automotive electronics, GaN devices, system-level ESD and emerging technologies.
- A new learning gateway: Registered participants get access to an online pre-conference tutorial covering ESD fundamentals, device physics and protection-circuit design — opening a specialised field to students and engineers beyond the traditional expert circle.
NE SCIENCE & TECHNOLOGY BUREAU
BENGALURU, AUG 27
What if the next threat to India’s semiconductor ambitions is not a shortage of chips — but an invisible electrical spark capable of silently destroying one?
As India accelerates its semiconductor manufacturing, chip-design and electronics ambitions, the spotlight is increasingly shifting from merely making smaller and faster chips to making them reliable, robust and capable of surviving increasingly complex operating environments.
That is precisely where electrostatic discharge (ESD) — often invisible and seemingly innocuous — becomes a formidable engineering challenge.
Against this backdrop, the 7th India ESD Workshop (InEW 2026) at the Indian Institute of Science (IISc), Bengaluru, on September 7-8 is set to bring students, researchers, semiconductor engineers and international experts together to examine one of the least visible but most consequential threats to modern electronics.
The workshop has evolved from IISc’s efforts, begun in 2015, to address gaps in ESD design, testing and technology expertise in India. The previous edition drew more than 250 senior semiconductor-industry engineers, while the initiative has developed collaborations with major global semiconductor and technology companies.
When a tiny spark becomes a billion-dollar problem
Why should students of VLSI, microelectronics and semiconductor engineering care about something they cannot even see?
Because as semiconductor devices become smaller, denser and more interconnected, protecting them from electrostatic discharge becomes increasingly complex. IISc describes ESD reliability and the design of ESD-safe chips as crucial throughout semiconductor design, development, testing and manufacturing.
The 2026 workshop therefore goes well beyond conventional chip-design discussions.
Its technical programme will examine advanced CMOS technologies including FinFETs, nanowires and nanosheets; emerging 2D, RRAM, neuromorphic and quantum devices; 2.5D and 3D ICs; through-silicon vias (TSVs); backside power delivery; automotive and RF technologies; ESD testing; device and system modelling; ESD CAD and verification; GaN power devices and system-level ESD.
For students entering the semiconductor ecosystem, the significance is unmistakable: the workshop offers a window into the engineering problems that emerge when a chip moves from a schematic on a computer screen to an actual product.
Where academia meets the semiconductor battlefield
The workshop is being positioned not simply as a conference of technical presentations but as a meeting ground between academic research, industrial challenges and emerging talent.
The 2026 programme features keynote talks, more than 30 technical talks, more than 20 poster presentations, a panel session and industry interaction, with an expected participation of more than 250 attendees.
Its poster sessions are designed to put research directly into conversation, allowing participants to question presenters and engage with work on electrostatic-discharge science. Industry sessions will focus on ESD-induced bottlenecks in cutting-edge semiconductor technologies and products, while panel discussions will examine emerging technological challenges and the role academia must play over the coming decade.
A dedicated Young Researchers Meet will further open conversations around research opportunities in leading R&D laboratories and academic institutions in India.
This academia-industry interface assumes particular importance as India expands semiconductor manufacturing, develops new fabs, grows chip-design centres and sees more startups move towards complete product development. IISc says this changing ecosystem makes specialised ESD expertise increasingly relevant.
The classroom comes before the conference hall
Perhaps the most education-focused feature of InEW 2026 is its effort to lower the entry barrier into a highly specialised field.
Registered participants will receive access to an online pre-conference tutorial on On-Chip ESD Device & Circuit Design. The tutorial begins August 30 and is designed to provide the foundations required to understand the workshop’s advanced technical sessions.
The programme covers 14 hours of structured learning across three modules: four hours on fundamentals of ESD and ESD design, six hours on high-current device physics under ESD conditions, and four hours on ESD protection-circuit design concepts and strategies. Topics include HBM, CDM and MM testing, TLP characterisation, ESD design windows, diodes, SCRs, ggNMOS, BJT, DeMOS/LDMOS and different protection architectures.
The initiative directly addresses a problem acknowledged by the organisers: ESD device physics and circuit-design expertise remains a niche area, and participants without a strong foundation can find highly technical workshop sessions difficult to follow.
For students, that makes the tutorial more than a preparatory lecture series. It can serve as an entry ramp into a specialised semiconductor discipline that is rarely taught in depth outside focused research and industry environments.
Training India’s semiconductor talent before the next chip wave
The larger educational significance of InEW 2026 lies in its timing.
India’s semiconductor aspirations will require more than fabrication plants and investment. They will require engineers who understand the physics, design constraints, reliability challenges and testing methodologies that determine whether a chip works reliably outside the laboratory.
That is why the workshop’s emphasis on ESD reliability assumes strategic importance.
The organisers envision InEW as a platform to increase ESD awareness among VLSI and microelectronics engineers and academics, connect engineers with global ESD experts, promote teaching and research, and strengthen academia-industry partnerships.
The 2026 programme also looks beyond today’s technologies. It examines ESD challenges in 3D integration, advanced packaging, backside power delivery, quantum and neuromorphic technologies, automotive electronics and GaN power ICs — areas likely to shape the next generation of electronic systems.
In that sense, the workshop is asking an unusually important education question: Can India build a semiconductor workforce that understands not only how to design the chip, but also how to make it survive?
The answer may determine how far India’s chip ambitions travel from the drawing board to dependable products.
Event: 7th India ESD Workshop (InEW 2026)
Dates: September 7-8, 2026
Venue: Indian Institute of Science, Bengaluru
Pre-conference tutorial: Online, beginning August 30
Registration: Open; official workshop registration is available through the InEW platform.
India ESD Workshop 2026 — official website
